package puf

import chisel3._
import chisel3.util._
import chisel3.experimental._

import puf._ 
import puf.PUF_Constants._


class top extends Module{
    val io = IO( new Bundle{
        val out =   new PUF_Core_Output_Ports
    } )

    val M_Core          =   Module(new core)

    val the_clock       =   Wire(Clock())
    val M_Clk_Divider   =   Module(new clk_divider)
    M_Clk_Divider.io.clk    :=  clock
    M_Clk_Divider.io.rst_p  :=  reset.asBool
    the_clock               :=  M_Clk_Divider.io.clk_div 

    M_Core.clock    :=  the_clock
    M_Core.io.out   <>  io.out

}

class core extends Module{
    val io = IO( new Bundle{
        val out =   new PUF_Core_Output_Ports
    } )

    val M_PUF_Core      =   Module(new PUF_Core2)

    val the_clock       =   Clk_Divider()

    M_PUF_Core.io.clk.Clk   :=  the_clock
    M_PUF_Core.io.in.Start  :=  true.B 
    M_PUF_Core.io.in.Data   :=  Cat(    VecInit(Seq.fill(1)( 1.U )).asUInt,
                                        VecInit(Seq.fill(65)( 0.U )).asUInt,
                                        VecInit(Seq.fill(12)( 0.U )).asUInt,
                                        VecInit(Seq.fill(60)( 1.U )).asUInt,
                                        VecInit(Seq.fill(72)( 1.U )).asUInt )
     //"hAAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA_AAAA".U 

    io.out.Data_in          :=  M_PUF_Core.io.out.Data_in
    io.out.Ena_in           :=  M_PUF_Core.io.out.Ena_in
    io.out.Ena_out          :=  M_PUF_Core.io.out.Ena_out
    io.out.Clk_in           :=  (M_PUF_Core.io.out.Clk_in && the_clock.asUInt.asBool)
    io.out.Clk_out          :=  (M_PUF_Core.io.out.Clk_out && the_clock.asUInt.asBool)

}